This invention relates to the control of data transfer between main storage and high speed external cabling.
Processor-to-I/O devices and processor-to-processor communication is well known in the prior art. Prior to this invention, communication speeds for IBM peripherals were limited to 4.5 MBytes/sec when using the standard IBM System/370 OEMI channel.
A newly proposed American National Standards Institute (ANSI) X3T9.3 link for information handling referred to as High Performance Parallel Interface (HIPPI, formerly referred to as High Speed Channel or HSC and HPPI has been proposed for peak rates of 800 or 1,600 Mbit/sec between data processing equipment using multiple twisted-pair copper cabling at distances up to 25 meters. A copy of this standard is provided as Appendix A.
A uniprocessor system that includes a system controller (SC) at the focal point in the system, a main storage (MS) including a main storage controller (MSC), a channel processor (CH) and one central processor (CP) is well known. Also multiprocessor systems having multiple system controllers (SC) and associated main storage, channel processors and multiple central processors are known.
An expanded storage such as paging storage is also well known. Brown et al. U.S. Pat. No. 4,476,524 teaches providing an independent data bus path between a random access page storage (PS) and a main storage where this independent data bus does not pass through any channel processor or central processor. Page data transfers on the independent data bus can be controlled either asychronously by a channel processor or synchronously by a central processor (independent of any CH operation). Novel CP instructions enable the CP to synchronously control the transfer of pages in either direction on the independent bus.